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Design Verification Engineer

役職名: Design Verification Engineer
雇用形態: 正社員
勤務地:
職種: エンジニアリング・製造
求人番号: PR/156117
求人情報掲載日: 2023/10/18 15:23
Job Descriptions:
  • Defining, documenting, executing and reporting the overall IP’s.
  • Driving technical innovation to enhance capabilities in IP validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.
  • Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives.
  • Developing knowledge of building verification environment - testbench (scoreboard, monitor, agent) at IP and SoC level (reuse from IP level), building of block level module when needed.
  • Supporting issues on customer platforms as requested by customer support teams.
 
Job Requirements
  • Bachelor’s or master’s degree majoring in Electrical & Electronics Engineering, Computer Science or related field.
  • Good understanding of Verilog / System Verilog.
  •  Good understanding on UVM, coverage based verification and constraint random verification.
  • Advance verification methods - formal property verification is a plus
  • Exposure to high speed serial interfaces such as PCIe and USB
  • Minimum have 4 years working experience.