JOB DESCRIPTIONS:
- Defining, documenting, executing and reporting the overall IP’s
- Driving technical innovation to enhance capabilities in IP validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives
- Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives
- Developing knowledge of building verification environment - testbench (scoreboard, monitor, agent) at IP and SoC level (reuse from IP level), building of block level module when needed
- Supporting issues on customer platforms as requested by customer support teams
JOB REQUIREMENTS:
- Bachelor’s or master’s degree majoring in EE, CS or related field.
- Good understanding of Verilog / System verilog
- Good understanding on UVM, coverage based verification and constraint random verification
- Advance verification methods - formal property verification is a plus
- Exposure to high speed serial interfaces such as PCIe and USB
- Minimum have 4 years relevant working experience